Integrated circuits and other electronic devices can include input and/or output (I/O) connections for transmitting and receiving signals. As signal transmission speeds have increased, impedance matching has become an increasingly important feature in such devices. Matching impedance with external package and/or circuit board traces can improve the signal integrity and performance of both a signal transmitter and receiver.
In order to match signal line impedance, I/O circuits can include variable impedance circuits that can be adjusted as needed to match a sensed reference impedance value. Such circuits typically include a pull-up array of impedance devices (e.g., resistors) and/or a pull-down array of impedance devices (e.g., resistors). By selectively enabling such impedance devices, the impedance presented at the I/O can be calibrated to provide a target impedance.
One circuit that can be used in calibrating I/Os is a variable impedance sense (VIS) circuit. A VIS circuit can be used in I/O circuits to match the impedance of pull-up and pull-down arrays to an impedance of an external trace by sensing the resistance of an external reference impedance (e.g., reference resistor). The accuracy of impedance sense and matching circuit can be limited by the architecture and various error sources.
To better understand various features of the disclosed embodiments, a conventional VIS circuit will now be described with reference to FIG. 11 (BACKGROUND ART #1).
A VIS circuit 1100 can include an external calibrating resistor RQ that is utilized to calibrate pull-up (PU) arrays 1102-0 and 1102-1, as well as a pull-down (PD) array 1104. PU arrays (1102-0 and 1102-1) and PD array 1104 are understood to be replicas of PU and PD arrays of actual I/O circuits (not shown) for which impedance matching is employed.
Each PU array and PD array can be composed of several pull-up and pull-down legs arranged in parallel. Each leg can represent a unit resistance, which can be established by a combination of transistors and/or a resistor, for example. An impedance of a PU array or PD array can be set by turning on the appropriate number of legs in parallel. FIG. 11 shows a digital count value (pu_dac[k:0] and pd_dac[k:0]) for both PU and PD arrays, respectively.
The VIS circuit 1100 also shows a switch circuit 1106. A switch circuit 1106 can selectively connect a reference voltage Vref or a voltage generated by PU/PD arrays 1102-1/1104 to one input (−) of a high gain comparator 1108 and a voltage generated by PU arrays 1102-0/RQ to another input (+) of the comparator 1108. The switch circuit 1106 shown includes two switch elements PD_EN and PU_EN.
Comparator 1108 has an output connected to a comparator register 1110. A comparator register 1110 can store an output value generated by comparator 1108.
The VIS circuit 1100 of FIG. 11 includes a calibration loop 1112 for a PU array as well as a calibration loop 1114 for a PD array. Further, the VIS circuit 1100 generates impedance matching values utilizing a successive approximation register (SAR) technique, and so includes SAR/counters (SAR/Counter) 1116-0 and 1116-1 for both such loops (1112 and 1114). A resulting value generated in the SAR/Counters 1116-0 and 1116-1 can be stored in update registers 1118-0 and 1118-1, respectively.
As is well understood, in a successive approximation technique, a “most” significant impedance leg can be switched into the circuit to create a voltage divider in combination with a reference impedance (e.g., RQ). A resulting voltage generated can be compared against a reference voltage. If the voltage is greater than the reference voltage (as determined by a comparator) a most significant bit can be set to a particular value (e.g., 1 or 0). In a following cycle, a next significant impedance leg can be switched into the circuit to determine the value of the next most significant bit. This can continue until a final code is generated.
In the arrangement of FIG. 11, SAR/Counters (1116-0 and 1116-1) can operate as successive approximation registers or as up/down counters based on the mode of operation and the comparator output. The particular mode of operation can be established by control block 1120.
In an initial calibration cycle, a control block 1120 operates SAR/Counters (1116-0 and 1116-1) as successive approximation registers. However, in an update cycle (described in more detail below), SAR/Counters (1116-0 and 1116-1) can operate as up and/or down counters.
Final codes generated by VIS circuit 1100 (pucode[k:1] and pdcode[k:1]) can be provided to other I/O circuits via final update registers 1122-0 and 1122-1. As shown in FIG. 11, final codes (pu_dac[k:1] and pd_dac[k:1]) can be generated by dropping a least significant bit (pu_dac[0] and pd_dac[0]) of a code stored in update registers 1118-0 and 1118-1, respectively.
The operation of the conventional VIS circuit 1100 will now be described.
A VIS circuit 1100 can be conceptualized as including two closed loops; one for the PU array calibration 1112 and another for the PD array calibration 1114. Each loop can include a resistive voltage divider digital-to-analog converter (DAC) and analog-to-digital converter (ADC). In the case of PU loop 1112, the DAC is formed by PU array 1102-0, which receives a digital code (pu_dac[k:0]), and reference resistor RQ, and provides a resulting analog voltage on reference node 1124. In the case of PD loop 1114, the DAC is formed by PU array 1102-1, which receives a digital code (pu_dac[k:0]) and PD array 1104, which receives a digital code (pd_dac[k:0]), and provides a resulting analog voltage on reference node 1126.
In the case of PU loop 1112, the ADC is an SAR type ADC formed by comparator 1108, comparator register 1110, and SAR/Counter 1116-0, as controlled by control block 1120. Similarly, in the case of PD loop 1114, the ADC is an SAR type ADC formed by comparator 1108, comparator register 1110, and SAR/Counter 1116-1, as controlled by control block 1120.
In a calibration of the PU loop 1112, VIS circuit 1100 can determine a binary output code (pucode[k:1]) for PU arrays in the device by calibrating PU array 1102-0 against external reference resistor RQ. In a calibration of PD loop 1114, VIS circuit 1100 can determine a binary output code (pdcode[k:1) for PD arrays in the device by calibrating PD array 1104 against an already calibrated PU array 1102-1. That is, once a calibrated pull-up code (pu_dac[k:0]) has been generated, such a code can be applied to PU array 1102-1, to enable it to act as a reference resistor for PD array 1104.
Initially, a PU loop 1112 can be enabled and a PD loop 1114 can be disabled. In such a state, switch element PU_EN can be closed (i.e., low impedance) and switch element PD_EN can be open (i.e., high impedance). An output of the PU voltage divider (1102-0/RQ) on reference node 1124 can be connected to a positive terminal of comparator 1108 and a reference voltage (Vref) can be connected to a negative terminal of comparator 1108. Resulting outputs of the comparator C1 can be used by SAR/Counter 1116-0 in an SAR type binary search algorithm to determine binary output code for the PU array (pu_dac[k:0]). In such an operation, comparator 1108 and SAR/Counter 1116-0 can act as an SAR ADC, which quantizes the analog input (output of the PU voltage divider) one bit (e.g., reference resistor leg) at a time. For each bit (starting from the MSB of pu_dac[k:0]), the ADC turns on the bit and checks the output of the DAC (PU voltage divider). If the output of comparator 1108 is HIGH, the bit can be turned off and the next bit can be turned on. If the output of comparator 1108 is LOW, a bit can be left on and the next bit can be turned on. This process can be repeated until all (in this case k+1) bits of the pull-up binary code (pu_dac[k:0]) have been determined. A final pull-up binary code can represent the number of pull-up legs required to match the impedance of PU array 1102-0 to the external resistor RQ.
Once PU array 1102-0 has been calibrated, the resulting code stored in update register 1118-0 can be output to reference PU array 1102-1, and PU loop 1112 can be disabled. Subsequently, PD loop 1114 can be enabled and the same procedure (SAR technique) can be used to calibrate PD array 1104. Accordingly, switch PD_EN can be closed and switch PU_EN can be open. An output of the PD voltage divider (1102-1/1104) at reference node 1126 can be connected to a negative terminal of comparator 1108 and node 1124 can be connected to a positive terminal of comparator 1108. A final pull-down binary code (pd_dac[k:0]) can be stored in update register 1118-1, and can represent the total number of pull-down legs required to match the impedance of PD array 1104 to calibrated PU array 1102-1. This can complete an initial calibration cycle.
However, while one set of calibration codes can provide an initial impedance match for I/Os of a device, operating conditions can result in changes (i.e., drift) in circuit components. In order to account for the variations in temperature and voltage the pull-up and pull-down binary output codes (pu_dac [k:0] and pd_dac [k:0]) can be updated every “P” number of clock cycles. Such updates can be 1 bit updates that introduce a maximum of 1 LSB in either an up direction (increment) or down direction (decrement). Such an operation can be an update cycle or update mode operation.
Referring still to FIG. 11, during an update mode operation, an SAR/Counter (1116-0 and/or 1116-1) can operate as an up-down counter according to an output of comparator 1108. A PU array 1102-0 can be updated first, with a resulting code being applied to PU array 1102-1. A PD array 1104 can then be updated. In more detail, during an update operation of a PU array 1102-0, if an output of comparator 1108 is ‘1’, indicating that there has been some decrease in the impedance of the PU array 1102-0, pull-up binary code (pu_dac[k:0]) can be decremented by 1. Conversely, if an output of comparator 1108 is ‘0’, indicating an increase in the impedance of PU array 1102-0, pull-up binary code (pu_dac[k:0]) can be incremented by 1. Once a pull-up binary code is updated, a pull-down binary code (pd_dac[k:0]) can be updated in the same general way. Such codes values can then be forwarded to actual I/Os of the device.
As noted briefly above, the arrangement of FIG. 11 shows an example in which a binary output code of k+1 bits is generated, but only k such bits are used as values to provide impedance matching at actual I/Os. That is, an LSB bit of binary output codes (pu_dac [k:0] and pd_dac [k:0]) can be dropped and the remaining k bits (pu_dac[k:1] and pd_dac[k:1] are stored in final update registers (1122-0 and 1122-1) and then provided to I/O driver circuits.
The dropping of an LSB can occur in order to reduce noise in a VIS circuit 1100. In the case of frequent update cycles, and especially for continuous updates (updates at every clock cycle), an LSB bit within each output code can toggle every update cycle (even if there is no significant temperature or voltage variation). Such a bit can be called a “chatter” bit. A chattering of an LSB bit can cause significant noise in a driver circuit and adversely affect its performance.
Accordingly, in cases where the noise due to the chattering bit dominates the accuracy gained by the 1 LSB, the LSB bit can be dropped and the remaining bits can be utilized to match impedance of actual I/O driver circuits. This can be the same as the I/O driver circuits getting all the bits, but with the last bit (LSB) being always ‘0’ (turned OFF). In FIG. 11, an LSB bit can be dropped only on a final code that is forwarded to I/O driver circuits and not on the code inside the VIS circuit. Thus, dropping of an LSB bit can have no effect on the general operation of the operation of calibration loops 1112 and 1114.
The conventional approach shown in FIGS. 11 and 14 is disclosed in commonly-owned co-pending U.S. patent application Ser. No. 11/138,823, filed on May 26, 2005, titled IMPEDANCE BUFFER METHOD, by Derek Yang. The contents of this application are incorporated by reference herein.
The conventional arrangement shown in FIG. 11 can provide advantageously precise matching between a PD array and a reference impedance (RQ). However, such an arrangement can have drawbacks in certain applications. First, matching may not be as precise between a PU array and RQ. Further, an input offset voltage can be a significant source of error in the VIS circuit 1100. In particular, in light of the quantization error introduced by dropping an LSB, the impact of an input offset upon performance can vary according to the polarity of the input offset.
One approach to addressing input offset is shown in commonly-owned co-pending U.S. patent application Ser. No. 11/540,831, filed on Sep. 28, 2006, titled VARIABLE IMPEDANCE SENSE ARCHITECTURE AND METHOD, by Vullaganti et al. One example of this approach is shown in FIGS. 12 and 13 (BACKGROUND ART #2). The contents of this application are incorporated by reference herein.
FIG. 12 is a block schematic diagram of a VIS circuit 1200. The operation of the circuit is shown in FIG. 13. In this particular example, when an input offset has a negative value, a generated SAR binary impedance setting value (code) can be incremented by one. Further, if a resulting incremented code has a LSB of “1”, the code can be incremented again prior to the LSB being dropped.
The above arrangement can provide advantageously precise matching between a PU array and a reference impedance (RQ). Further, error rates resulting from an input offset and subsequent quantization resulting from dropping the LSB can be addressed.
Referring now to FIG. 13, a conceptual operation of the VIS circuit of FIG. 12 is shown in a flow diagram. FIG. 13 shows an initial calibration cycle, as well as update operations described above. Within the flow diagram 1300, “STEP B1” refers to implementation of a binary search SAR technique during an initial calibration cycle. STEP B2 refers to the operation of, if needed, further incrementing a code prior to dropping an LSB. STEP B3 represents an up/down counter operation during an update operation. STEP B4 represents the operation of, if needed, further incrementing a code prior to dropping an LSB during an update operation.
While the above approach can provide clear advantages over conventional impedance sensing and matching, even greater improvements are desirable in some applications. In particular, some applications can require matching not only between a line (e.g., trace) impedance, but also a matching between a PU array and PD array. For example, some operational specifications can require that an impedance between a PU array and PD array, with respect to a reference impedance (RQ), be no more than 10%. At the same time, PU array and PD array impedance should vary by no more than 4%.
Thus, while an approach like that of FIGS. 11 and 12 can provide relatively good matching between a PD array and/or PU array to a reference impedance (RQ), such approaches may not meet a required tolerance of impedance matching between a PD array and PU array.
In approaches like those described above, during an update cycle, the compensation mechanism for impedance variations following an initial calibration involves changing the LSB of a code either 1 bit up or 1 bit down based on the output of the comparator. However, such compensation can occur even when there is no significant variation in the impedance, or when the variation is such that the error is actually reduced. Because the architectures like those above simply count 1 LSB up or down based on the output of the comparator, in certain cases an additional error of 1 LSB can be introduced during an update cycle. This is explained in detail below in FIGS. 14A to 14B.
FIG. 14A shows an example of the propagation of a worst-case error during the initial and update mode operations. The figure shows an example in which an input offset is positive. During the update mode operation of pull-down array codes (PD calibration), even when there is no significant variation in the resistance of the PD array, a control block can count one LSB up (see STEPB3). This count-up operation can increase pull-down impedance code error by 1 LSB. Further, a mismatch between a PU array and PD array can be 2 LSB as a result of the update mode operation.
FIG. 14B shows another example for the propagation of the worst-case error during the initial and update mode operations. In this example, pull-up array has a small/negligible variation moving towards the target resistance RQ. A control block can count one LSB down, further increasing the error, even though the variation is actually moving closer to a target resistance RQ. Further, a mismatch between a PU array and PD array can once again be 2 LSB as a result of this update mode operation.
These error rates are summarized in the table of FIG. 15.